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AD9281 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a dual channel 8-bit resolution cmos adc features complete dual matching adc low power dissipation: 225 mw (+3 v supply) single supply: 2.7 v to 5.5 v differential nonlinearity error: 0.1 lsb on-chip analog input buffers on-chip reference signal-to-noise ratio: 49.2 db over seven effective bits spurious-free dynamic range: C65 db no missing codes guaranteed 28-lead ssop functional block diagram 1v reference buffer qrefb irefb qreft ireft vref refsense iina iinb "i" adc qinb qina "q" adc q register i register three- state output buffer avdd avss clock dvdd dvss sleep select data 8 bits chip select AD9281 asynchronous multiplexer product description the AD9281 is a complete dual channel, 28 msps, 8-bit cmos adc. the AD9281 is optimized specifically for applica- tions where close matching between two adcs is required (e.g., i/q channels in communications applications). the 28 mhz sampling rate and wide input bandwidth will cover both narrow- band and spread-spectrum channels. the AD9281 integrates two 8-bit, 28 msps adcs, two input buffer amplifiers, an inte rnal voltage reference and multiplexed digital output buffers. each adc incorporates a simultaneous sampling sample-and- hold amplifier at its input. the analog inputs are buffered; no external input buffer op amp will be required in most applica- tions. the adcs are implemented using a multistage pipeline architecture that offers accurate performance and guarantees no missing codes. the outputs of the adcs are ported to a multi- plexed digital output buffer. the AD9281 is manufactured on an advanced low cost cmos process, operates from a single supply from 2.7 v to 5.5 v, and consumes 225 mw of power (on 3 v supply). the AD9281 input struc ture accepts either single-ended or differential signals, providing excellent dynamic performance up to and beyond 14 mhz nyquist input frequencies. product highlights 1. dual 8-bit, 28 msps adc a pair of high performance 28 msps adcs that are opti- mized for spurious free d ynamic performance are provided for encoding of i and q or diversity channel information. 2. low power complete cmos dual adc function consumes a low 225 mw on a single sup ply (on 3 v supply). the ad 9281 operates on supply voltages from 2.7 v to 5.5 v. 3. on-chip voltage reference the AD9281 includes an on-chip compensated bandgap voltage reference pin programmable for 1 v or 2 v. 4. on-chip analog input buffers eliminate the need for external op amps in most applications. 5. single 8-bit digital output bus the AD9281 adc outputs are interleaved onto a single output bus saving board space and digital pin count. 6. small package the AD9281 offers the complete integrated function in a compact 28-lead ssop package. 7. product family the AD9281 dual adc is pin compatible with a dual 10-bit adc (ad9201). rev. f
AD9281* product page quick links last content update: 02/23/2017 comparable parts view a parametric search of comparable parts. documentation application notes ? an-282: fundamentals of sampled data systems ? an-297: test video a/d converters under dynamic conditions ? an-302: exploit digital advantages in an ssb receiver ? an-345: grounding for low-and-high-frequency circuits ? an-501: aperture uncertainty and adc system performance ? an-715: a first approach to ibis models: what they are and how they are generated ? an-737: how adisimadc models an adc ? an-741: little known characteristics of phase noise ? an-756: sampled systems and the effects of clock phase noise and jitter ? an-835: understanding high speed adc testing and evaluation ? an-905: visual analog converter evaluation tool version 1.0 user manual ? an-935: designing an adc transformer-coupled front end data sheet ? AD9281: dual channel 8-bit resolution cmos adc data sheet tools and simulations ? visual analog reference materials technical articles ? correlating high-speed adc performance to multicarrier 3g requirements ? dnl and some of its effects on converter performance ? ms-2210: designing power supplies for high speed adc design resources ? AD9281 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all AD9281 engineerzone discussions. sample and buy visit the product page to see pricing options. technical support submit a technical question or find your regional support number. document feedback submit feedback for this data sheet. this page is dynamically generated by analog devices, inc., and inserted into this data sheet. a dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. this dynamic page may be frequently modified.
C2C AD9281Cspecifications (avdd = +3 v, dvdd = +3 v, f sample = 28 msps, vref = 2 v, inb = 0.5 v, t min to t max unless otherwise noted) parameter symbol min typ max units condition resolution 8 bits conversion rate f s 28 mhz (32 mhz at +25 c) dc accuracy differential nonlinearity dnl 0.1 lsb reft = 1.0 v, refb = 0.0 v integral nonlinearity inl 0.25 lsb differential nonlinearity (se) 1 dnl 0.2 1.0 lsb reft = 1.0 v, refb = 0.0 v integral nonlinearity (se) 1 inl 0.3 1.5 lsb zero-scale error, offset error e zs 1 3.2 % fs full-scale error, gain error e fs 1.2 5.4 % fs gain match 0.2 lsb offset match 1.2 lsb analog input input voltage range ain C0.5 avdd/2 v input capacitance c in 2p f aperture delay t ap 4n s aperture uncertainty (jitter) t aj 2p s aperture delay match 2 ps input bandwidth (C3 db) bw small signal (C20 db) 240 mhz full power (0 db) 245 mhz internal reference output voltage (1 v mode) vref 1 v refsense = vref output voltage tolerance (1 v mode) 10 mv output voltage (2 v mode) vref 2 v refsense = gnd output voltage tolerance (2 v mode) 15 mv load regulation (1 v mode) vref 10 35 mv 1 ma load current load regulation (2 v mode) 15 mv 1 ma load current power supply operating voltage avdd 2.7 3 5.5 v dvdd 2.7 3 5.5 v supply current i avdd 75 ma i dvdd 0.1 ma power consumption p d 225 260 mw power-down 16 mw stby = avdd, clock low power supply rejection psr 0.15 0.75 % fs dynamic performance 2 signal-to-noise and distortion sinad f = 3.58 mhz 46.4 49.1 db f = 14 mhz 48 db signal-to-noise snr f = 3.58 mhz 47.8 49.2 db f = 14 mhz 48.5 db total harmonic distortion thd f = 3.58 mhz C67.5 C49.5 db f = 14 mhz C60 db spurious free dynamic range sfdr f = 3.58 mhz 49.6 65 db f = 14 mhz 56 db two-tone intermodulation distortion 3 imd C58 db f = 44.9 mhz and 45.52 mhz differential phase dp 0.2 degree ntsc 40 ire mod ramp differential gain dg 0.08 % f s = 14.3 mhz crosstalk rejection C62 db rev. f
C3C AD9281 parameter symbol min typ max units condition dynamic performance (se) 1 signal-to-noise and distortion sinad f = 3.58 mhz 47.2 db signal-to-noise snr f = 3.58 mhz 48 db total harmonic distortion thd f = 3.58 mhz C55 db spurious free dynamic range sfdr f = 3.58 mhz C58 db digital inputs high input voltage v ih 2.4 v low input voltage v il 0.3 v dc leakage current i in 6 m a input capacitance c in 2p f logic output (with dvdd = 3 v) high level output voltage (i oh = 50 m a) v oh 2.88 v low level output voltage (i ol = 1.5 ma) v ol 0.095 v logic output (with dvdd = 5 v) high level output voltage (i oh = 50 m a) v oh 4.5 v low level output voltage (i ol = 1.5 ma) v ol 0.4 v data valid delay t od 11 ns mux select delay t md 7n s data enable delay t ed 13 ns c l = 20 pf. output level to 90% of final value data high-z delay t dhz 13 ns clocking clock pulsewidth high t ch 16.9 ns clock pulsewidth low t cl 16.9 ns pipeline latency 3.0 cycles notes 1 se is single ended input, reft = 1.5 v, refb = C0.5 v. 2 ain differential 2 v p-p, reft = 1.5 v, refb = C0.5 v. 3 imd referred to larger of two input signals. specifications subject to change without notice. clock input select input data output adc sample #2 adc sample #3 adc sample #4 adc sample #5 q channel output enabled i channel output enabled sample #1-3 q channel output sample #1-2 q channel output sample #1-1 q channel output sample #1-1 i channel output sample #1 q channel output sample #1 i channel output sample #2 q channel output t md t od adc sample #1 figure 1. adc timing rev. f
AD9281 C4C caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD9281 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. pin configuration top view (not to scale) AD9281 reft-q inb-q ina-q chip-select vref avdd refb-q refb-i avss refsense reft-i sleep ina-i inb-i dvss dvdd (lsb) d0 d1 d2 d3 d4 d5 d6 (msb) d7 select clock nc = no connect warning! esd sensitive device absolute maximum ratings* with respect parameter to min max units avdd avss C0.3 +6.5 v dvdd dvss C0.3 +6.5 v avss dvss C0.3 +0.3 v avdd dvdd C6.5 +6.5 v clk avss C0.3 avdd + 0.3 v digital outputs dvss C0.3 dvdd + 0.3 v aina, ainb avss C1.0 avdd + 0.3 v vref avss C0.3 avdd + 0.3 v refsense avss C0.3 avdd + 0.3 v reft, refb avss C0.3 avdd + 0.3 v junction temperature +150 c storage temperature C65 +150 c lead temperature 10 sec +300 c *stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum ratings for extended periods may effect device reliability. pin function descriptions p in no. name description 1 dvss digital ground 2 dvdd digital supply 3 4 5 d0 bit 0 (lsb) 6 d1 bit 1 7 d2 bit 2 8 d3 bit 3 9 d4 bit 4 10 d5 bit 5 11 d6 bit 6 12 d7 bit 7 (msb) 13 select hi i channel out, lo q channel out 14 clock clock 15 sleep hi power down, lo normal operation 16 ina-i i channel, a input 17 inb-i i channel, b input 18 reft-i top reference decoupling, i channel 19 refb-i bottom reference decoupling, i channel 20 avss analog ground 21 refsense reference select 22 vref internal reference output 23 avdd analog supply 24 refb-q bo ttom reference decoupling, q channel 25 reft-q top reference decoupling, q channel 26 inb-q q channel b input 27 ina-q q channel a input 28 chip-select hi-high impedance, lo-normal operation definitions of specifications integral nonlinearity (inl) integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale. the point used as zero occurs 1/2 lsb before the first code transi- tion. full scale is defined as a level 1 1/2 lsbs beyond the last code transition. the deviation is measured from the center of each particular code to the true straight line. differential nonlinearity (dnl, no missing codes) an ideal adc exhibits code transitions that are exactly 1 lsb apart. dnl is the deviation from this ideal value. it is often specified in terms of the resolution for which no missing codes (nmc) are guaranteed. rev. f
AD9281 C5C drvdd avss drvss drvss avdd avdd avss avss avdd refbs refbf avdd avss avdd avss avdd avss avdd avss in avdd avss avss avdd avdd avss avdd avss d. ina, inb e. reference f. refsense g. vref figure 2. equivalent circuits offset error the first transition should occur at a level 1 lsb above zero. offset is defined as the deviation of the actual first code transi- tion from that point. offset match the change in offset error between i and q channels. effective number of bits (enob) for a sine wave, sinad can be expressed in terms of the num- ber of bits. using the following formula, n = ( sinad C 1.76)/6.02 it is possible to get a measure of performance expressed as n , the effective number of bits. thus, effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured sinad. total harmonic distortion (thd) thd is the ratio of the rms sum of the first six harmonic com- ponents to the rms value of the measured input signal and is expressed as a percentage or in decibels. signal-to-noise ratio (snr) snr is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the nyquist frequency, excluding the first six harmonics and dc. the value for snr is expressed in decibels. spurious free dynamic range (sfdr) the difference in db between the rms amplitude of the input signal and the peak spurious signal. gain error the first code transition should occur for an analog value 1 lsb above nominal negative full scale. the last transition should occur for an analog value 1 lsb below the nominal positive full scale. gain error is the deviation of the actual difference be- tween first and last code transitions and the ideal difference between the first and last code transitions. gain match the change in gain error between i and q channels. pipeline delay (latency) the number of clock cycles between conversion initiation and the associated output data being made available. new output data is provided every rising clock edge. mux select delay the delay between the change in select pin data level and valid data on output pins. power supply rejection the specification shows the maximum change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit. aperture jitter aperture jitter is the variation in aperture delay for successive samples and is manifested as noise on the input to the a/d. aperture delay aperture delay is a measure of the sample-and-hold amplifier (sha) performance and is measured from the rising edge of the clock input to when the input signal is held for conversion. signal-to-noise and distortion (s/n+d, sinad) ratio s/n+d is the ratio of the rms value of the measured input sig- nal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for s/n+d is expressed in decibels. a. d0Cd9 b. three-state standby c. clk rev. f
AD9281 C6C Ctypical characteristic curves (avdd = +3 v, dvdd = +3 v, f s = 28 mhz (50% duty cycle), 2 v input span from C0.5 v to +1.5 v, 2 v internal reference unless otherwise noted) rev. f
AD9281 C7C clock frequency C hz 70 20 1.00e+06 1.00e+08 1.00e+07 thd C db 55 65 60 50 45 40 35 30 25 figure 9. thd vs. clock frequency temperature C 8c 1.013 1.012 1.008 C40 100 C20 v ref C volts 020406080 1.011 1.010 1.009 figure 10. voltage reference error vs. temperature clock frequency C mhz 185 032 4 power consumption C mw 8 1216 202428 220 210 200 190 240 230 225 215 205 235 195 figure 11. power consumption vs. clock frequency code 1.20e+07 1.00e+07 0.00e+00 n+1 nC1 hits n 8.00e+06 6.00e+06 4.00e+06 2.00e+06 12050 10000000 800 figure 12. grounded input histogram input frequency C hz 0 1.00e+06 amplitude C db C3 C6 C9 C12 C15 C21 1.00e+07 1.00e+08 1.00e+09 C24 C27 C18 figure 13. full power bandwidth input frequency C hz 50 1.00e+05 snr C db 45 40 35 30 25 1.00e+06 1.00e+07 1.00e+08 C0.5db C6db C20db figure 14. snr vs. input frequency (single-ended) rev. f
AD9281 C8C theory of operation the AD9281 integrates two a/d converters, two analog input buffers, an internal reference and reference buffer, and an out- put multiplexer. for clarity, this data sheet refers to the two converters as i and q. the two a/d converters simulta- neously sample their respective inputs on the rising edge of the input clock. the two converters distribute the conversion opera- tion over several smaller a/d sub-blocks, refining the conversion with progressively higher accuracy as it passes the result from stage to stage. as a consequence of the distributed conversion, each converter requires a small fraction of the 256 comparators used in a traditional flash-type 8-bit adc. a sample-and-hold function within each of the stages permits the first stage to oper- ate on a new input sample while the following stages continue to process previous samples. this results in a pipeline processing latency of three clock periods between when an input sample is taken and when the corresponding adc output is updated into the output registers. the AD9281 integrates input buffer amplifiers to drive the analog inputs of the converters. in most applications, these input amplifiers eliminate the need for external op amps for the input signals. the input structure is fully differential, but the sha common-mode response has been designed to allow the converter to readily accommodate either single-ended or differ- ential input signals. this differential structure makes the part capable of accommodating a wide range of input signals. the AD9281 also includes an on-chip bandgap reference and reference buffer. the reference buffer shifts the ground-referred reference to levels more suitable for use by the internal circuits of the converter. both converters share the same reference and reference buffer. this scheme provides for the best possible gain match between the converters while simultaneously minimizing the channel-to-channel crosstalk. each a/d converter has its own output latch, which updates on the rising edge of the input clock. a logic multiplexer, con- trolled through the select pin, determines which channel is passed to the digital output pins. the output drivers have their own supply, allowing the part to be interfaced to a variety of logic families. the outputs can be placed in a high impedance state using the chip select pin. the AD9281 has great flexibility in its supply voltage. the analog and digital supplies may be operated from 2.7 v to 5.5 v, independently of one another. analog input figure 16 shows an equivalent circuit structure for the analog input of one of the a/d converters. pmos source-followers buffer the analog input pins from the charge kickback problems normally associated with switched capacitor adc input struc- tures. this produces a very high input impedance on the part, allowing it to be effectively driven from high impedance sources. this means that the AD9281 could even be driven directly by a passive antialias filter. adc core +fs limit Cfs limit buffer buffer iina iinb v ref +fs limit = v ref +v ref/2 Cfs limit = v ref Cv ref/2 output word sha figure 16. equivalent circuit for AD9281 analog inputs the source followers inside the buffers also provide a level-shift function of approximately 1 v, allowing the AD9281 to accept inputs at or below ground. one consequence of this structure is that distortion will result if the analog input comes within 1.4 v of the positive supply. for optimum high frequency distortion performance, the analog input signal should be centered accord- ing to figure 27. the capacitance load of the analog input pin is 4 pf to the analog supplies (avss, avdd). full-scale setpoints may be calculated according to the following algorithm (v ref may be internally or externally generated): Cf s = v ref C (v ref /2) +f s = v ref + (v ref /2) v span = v ref 10.0 0.0e+0 snr C db 0.0 C10.0 C20.0 C30.0 C40.0 C50.0 C60.0 C70.0 C80.0 C90.0 C100.0 C110.0 2.0e+6 4.0e+6 6.0e+6 8.0e+6 10.0e+6 12.0e+6 14.0e+6 fund 5th 6th 4th 7th 3rd 9th 2nd 8th figure 15a. simultaneous operation of i and q channels 10.0 0.0e+0 snr C db 0.0 C10.0 C20.0 C30.0 C40.0 C50.0 C60.0 C70.0 C80.0 C90.0 C100.0 C110.0 2.0e+6 4.0e+6 6.0e+6 8.0e+6 10.0e+6 12.0e+6 14.0e+6 fund 5th 4th 7th 3rd 2nd 8th 6th figure 15b. simultaneous operation of i and q channels rev. f
AD9281 C9C the AD9281 can accommodate a variety of input spans be- tween 1 v and 2 v. for spans of less than 1 v, expect a propor- tionate degradation in snr. use of a 2 v span will provide the best noise performance. 1 v spans will provide lower distortion when using a 3 v analog supply. users wishing to run with larger full-scales are encouraged to use a 5 v analog supply (avdd). single-ended inputs: for single-ended input signals, the signal is applied to one input pin and the other input pin is tied to a midscale voltage. this midscale voltage defines the center of the full-scale span for the input signal. example: for a single-ended input range from 0 v to 1 v applied to iina, we would configure the converter for a 1 v reference (see figure 17) and apply 0.5 v to iinb. i or qreft i or qrefb iina iinb vref ref sense 0.1mf 10mf 0.1mf 0.1mf 0.1mf AD9281 0.1mf 10mf 10mf midscale voltage = 0.5v (1v) 1v 0v input 5k v 5k v figure 17. example configuration for 0 vC1 v single- ended input signal note that since the inputs are high impedance, this reference level can easily be generated with an external resistive divider with large resistance values (to minimize power dissipation). a decoupling capacitor is recommended on this input to minimize the high frequency noise-coupling onto this pin. decoupling should occur close to the adc. differential inputs use of differential input signals can provide greater flexibility in input ranges and bias points, as well as offering improvements in distortion performance, particularly for high frequency input signals. users with differential input signals will probably want to take advantage of the differential input structure of the AD9281. performance is still very good for single-ended inputs. convert- ing a single-ended input to a differential signal for application to the converter is probably only worth considering for very high frequency input signals. ac-coupled inputs if the signal of interest has no dc component, ac coupling can be easily used to define an optimum bias point. figure 18 illustrates one recommended configuration. the voltage chosen for the dc bias point (in this case the 1 v reference) is applied to both iina and iinb pins through 1 k w resistors (r1 and r2). iina is coupled to the input signal through capacitor c1, while iinb is decoupled to ground through capacitor c2. 0.1mf 10mf 0.1mf 0.1mf analog input 1.0 m f 0.1mf 1kv 1.5v 0.5v i or qreft i or qrefb iina iinb vref AD9281 refsense figure 18. example configuration for 0.5 vC1.5 v ac coupled single-ended inputs transformer coupled inputs another option for input ac coupling is to use a transformer. this not only provides dc rejection, but also allows truly differ- ential drive of the AD9281s analog inputs, which will provide the optimal distortion performance. figure 19 shows a recom- mended transformer input drive configuration. resistors r1 and r2 define the termination impedance of the transformer cou- pling. the center tap of the transformer secondary is tied to the common-mode voltage, establishing the dc bias point for the analog inputs. 0.1m f10 m f 0.1mf 0.1mf common mode voltage 0.1mf 10mf r1 r2 i or qreft i or qrefb iina iinb AD9281 qinb qina refsense vref figure 19. example configuration for transformer coupled inputs crosstalk: the internal layout of the AD9281, as well as its pinout, was configured to minimize the crosstalk between the two input signals. users wishing to minimize high frequency crosstalk should take care to provide the best possible decoupling for input pins (see figure 20). r and c values will make a pole dependant on antialiasing requirements. decoupling is also required on reference pins and power supplies (see figure 21). qina qinb iina iinb AD9281 figure 20. input loading dvdd i or qreft i or qrefb avdd 0.1mf 10mf 0.1 m f10 m f AD9281 0.1 mf 0.1 mf 0.1mf 10mf v analog v digital figure 21. reference and power supply decoupling rev. f
AD9281 C10C reference and reference buffer the reference and buffer circuitry on the AD9281 is configured for maximum convenience and flexibility. an illustration of the equivalent reference circuit is show in figure 26. the user can select from five different reference modes through appropriate pin-strapping (see table i below). these pin strapping options cause the internal circuitry to reconfigure itself for the appropri- ate operating mode. table i. table of modes mode input span refsense pin figure 1 v 1 v vref 22 2 v 2 v agnd 23 programmable 1 + (r1/r2) see figure 24 external = external ref avdd 25 1 v mode (figure 22) provides a 1 v reference and 1 v input full scale. recommended for applications wishing to optimize high frequency performance, or any circuit on a supply voltage of less than 4 v. the part is placed in this mode by shorting the refsense pin to the vref pin. i or qreft i or qrefb iina iinb vref 0.1m f10 m f 0.1mf 0.1mf 0.1mf AD9281 0.1mf 10mf 10mf 1v 0v qinb qina 5kv 5k v refsense 1v 0v 1v figure 22. 0 v to 1 v input 2 v mode (figure 23) provides a 2 v reference and 2 v input full scale. recommended for noise sensitive applications on 5 v suppli es. the part is placed in 2 v reference mode by ground- ing (shorting to avss) the refsense pin. i or qreft i or qrefb iina iinb vref 0.1m f10 m f 0.1mf 0.1mf 0.1mf AD9281 0.1mf 10mf 10mf 2v 0v qinb qina 5kv 5k v refsense 2v 0v figure 23. 0 v to 2 v input externally set voltage mode (figure 24) this mode uses the on-chip reference, but scales the exact reference level though the use of an external resistor divider network. vref is wired to the top of the network, with the refsense wired to the tap point in the resistor divider. the reference level (and input full scale) will be equal to 1 v (r1 + r2)/r1. this method can be used for voltage levels from 0.7 v to 2.5 v. i or qreft i or qrefb vref 0.1m f10 m f 0.1mf 0.1mf AD9281 refsense + C avss 0.1 mf 1mf r2 r1 1v vref = 1 + r2 r1 + C figure 24. programmable reference external reference mode (figure 25) in this mode, the on- chip reference is disabled, and an external reference applied to the vref pin. this mode is achieved by tying the refsense pin to avdd. 1v ext reference avdd i or qreft i or qrefb iina iinb vref 0.1m f10 m f 0.1mf 0.1mf 0.1mf AD9281 0.1mf 10mf 10mf 1v 0v qinb qina 5kv 5k v refsense 1v 0v figure 25. external reference reference buffer the reference buffer structure takes the voltage on the vref pin and level-shifts and buffers it for use by various sub-blocks within the two a/d converters. the two converters share the same reference buffer amplifier to maintain the best possible gain match between the two converters. in the interests of minimizing high frequency crosstalk, the buffered references for the two converters are separately decoupled on the irefb, ireft, qrefb and qreft pins, as illustrated in figure 26. rev. f
AD9281 C11C qreft qrefb ireft 0.1 m f10 m f 0.1 mf 0.1 mf AD9281 refsense avss 1v 0.1 mf 10mf irefb vref 0.1 mf 0.1 mf 10kv 10kv adc core internal control logic 0.1 mf 1.0 mf figure 26. reference buffer equivalent circuit and external decoupling recommendation for best results in both noise suppression and robustness against crosstalk, the 4-capacitor buffer decoupling arrangement shown in figure 26 is recommended. this decoupling should C3 C0.5 thd C db C13 C23 C33 C43 C53 C63 C73 0 0.5 1 1.5 cml C v 2v 1v a. differential input, 3 v supplies C35 C0.5 thd C db C40 C45 C50 C55 C60 C65 C70 0 0.5 1 1.5 cml C v 2 2.5 1v 2v b. differential input, 5 v supplies figure 27. thd vs. cml input span and power supply (analog input = 1 mhz) C15 C0.5 thd C db C25 C35 C45 C55 C65 0 0.5 1 1.5 cml C v 2v 1v c. single-ended input, 3 v supplies C15 C0.5 thd C db C25 C35 C45 C55 C65 0 0.5 1 1.5 cml C v 2v 1v 2 2.5 d. single-ended input, 5 v supplies feature chip capacitors located close to the converter ic. the capacitors are connected to either ireft/irefb or qreft/ qrefb. a connection to both sides is not required. common-mode performance attention to the common-mode point of the analog input volt- age can improve the performance of the AD9281. figure 27 illustrates thd as a function of common-mode voltage (center point of the analog input span) and power supply. inspection of the curves will yield the following conclusions: 1. an AD9281 running with avdd = 5 v is the easiest to drive. 2. differential inputs are the most insensitive to common-mode voltage. 3. an AD9281 powered by avdd = 3 v and a single ended input, should have a 1 v span with a common-mode voltage of 0.75 v. rev. f
AD9281 C12C select when the select pin is held low, the output word will present the q level. when the select pin is held high, the i level will be presented to the output word (see figure 1). the AD9281s select and clock pins may be driven by a com- mon signal source. the data will change in 5 ns to 11 ns after the edges of the input pulse. the user must make sure the inter- face latches have sufficient hold time for the AD9281s delays (see figure 28). clock data i latch clock data q latch clk data out select i processing q processing clock source figure 28. typical de-mux connection applications using the AD9281 for qam demodulation qam is one of the most widely used digital modulation sche mes in digital communication systems. this modulation technique can be found in both fdma as well as spread spectrum (i.e., cdma) based systems. a qam signal is a carrier frequency which is both modulated in amplitude (i.e., am modulation) and in phase (i.e., pm modulation). at the transmitter, it can be generated by independently modulating two carriers of iden- tical frequency but with a 90 phase difference. this results in an inphase (i) carrier component and a quadrature (q) carrier component at a 90 phase shift with respect to the i component. the i and q components are then summed to provide a qam signal at the specified carrier or if frequency. figure 29 shows a typical analog implementation of a qam modulator using a dual 10-bit dac with 2 interpolation, the ad9761. a qam signal can also be synthesized in the digital domain thus requir- ing a single dac to reconstruct the qam signal. the ad9853 is an example of a complete (i.e., dac included) digital qam modulator. 0 90 dsp or asic 10 carrier frequency nyquist filters to mixer quadrature modulator ad9761 iout qout figure 29. typical analog qam modulator architecture digital inputs and outputs each of the AD9281 digital control inputs, chip select, clock, select and sleep are referenced to avdd and avss. switching thresholds will be avdd/2. the format of the digital output is straight binary. a low power mode feature is provided such that for stby = high and the clock disabled, the static power of the AD9281 will drop below 22 mw. clock input the AD9281 clock input is internally buffered with an inverter powered from the avdd pin. this feature allows the AD9281 to accommodate either +5 v or +3.3 v cmos logic input sig- nal swings with the input threshold for the clk pin nominally at avdd/2. the pipelined architecture of the AD9281 operates on both rising and falling edges of the input clock. to minimize duty cycle variations the logic family recommended to drive the clock input is high speed or advanced cmos (hc/hct, ac/act) logic. cmos logic provides both symmetrical voltage threshold levels and sufficient rise and fall times to support 28 msps operation. running the part at slightly faster clock rates may be possible, although at reduced performance levels. conversely, some slight performance improvements might be realized by clocking the AD9281 at slower clock rates. the power dissipated by the output buffers is largely propor- tional to the clock frequency; running at reduced clock rates provides a reduction in power consumption. digital outputs each of the on-chip buffers for the AD9281 output bits (d0Cd9) is powered from the dvdd supply pin, separate from avdd. the output drivers are sized to handle a variety of logic families while minimizing the amount of glitch energy generated. in all cases, a fan-out of one is recommended to keep the capaci tive load on the output data bits below the specified 20 pf level. for dvdd = 5 v, the AD9281 output signal swing is compat- ible with both high speed cmos and ttl logic families. for ttl, the AD9281 on-chip, output drivers were designed to support several of the high speed ttl families (f, as, s). for applications where the clock rate is below 28 msps, other ttl families may be appropriate. for interfacing with lower voltage cmos logic, the AD9281 sustains 28 msps operation with dvdd = 3 v. in all cases, check your logic family data sheets for compatibility with the AD9281s specification table. a 2 ns reduction in output delays can be achieved by limiting the logic load to 5 pf per output line. three-state outputs the digital outputs of the AD9281 can be placed in a high impedance state by setting the chip select pin to high. this feature is provided to facilitate in-circuit testing or evaluation. rev. f
AD9281 C13C analog circuits digital logic ics dv a a d dvss avss a b i a i d avdd dvdd logic supply d a v in c stray c stray gnd a = analog d = digital adc ic digital circuits a a figure 31. ground and power consideration these characteristics result in both a reduction of electro- magnetic interference (emi) and an overall improvement in performance. it is important to design a layout that prevents noise from cou- pling onto the input signal. digital signals should not be run in parallel with the input signal traces and should be routed away from the input circuitry. separate analog and digital grounds should be joined together directly under the AD9281 in a solid ground plane. the power and ground return currents must be carefully managed. a general rule of thumb for mixed signal layouts dictates that the return currents from digital cir- cuitry should not pass through critical analog circuitry. transients between avss and dvss will seriously degrade performance of the adc. if the user cannot tie analog ground and digital ground together at the adc, he should consider the configuration in figure 32. another input and ground technique is shown in figure 32. a separate ground plane has been split for rf or hard to manage signals. these signals can be routed to the adc differentially or single ended (i.e., both can either be connected to the driver or rf ground). the adc will perform well with several hundred mv of noise or signals between the rf and adc analog ground. data analog ground digital ground logic adc ain bin rf ground figure 32. rf ground scheme at the receiver, the demodulation of a qam signal back into its separate i and q components is essentially the modulation process explain above but in the reverse order. a common and traditional implementation of a qam demodulator is shown in figure 30. in this example, the demodulation is performed in the analog domain using a dual, matched adc and a quadra- ture demodulator to recover and digitize the i and q baseband signals. the quadrature demodulator is typically a single ic containing two mixers and the appropriate circuitry to generate the necessary 90 phase shift between the i and q mixers local oscillators. before being digitized by the adcs, the mixed down baseband i and q signals are filtered using matched ana- log filters. these filters, often referred to as nyquist or pulse- shaping filters, remove images-from the mixing process and any out-of-band. the characteristics of the matching nyquist filters are well defined to provide optimum signal-to-noise (snr) performance while minimizing intersymbol interference. the adcs are typically simultaneously sampling their respective inputs at the qam symbol rate or, m ost often, at a multiple of it if a digital filter follows the adc. oversampling and the use of digital filtering eases the implementation and complexity of the analog filter. it also allows for enhanced digital processing for both carrier and symbol recovery and tuning purposes. the use of a dual adc such as the AD9281 ensures excellent gain, offset, and phase matching between the i and q channels. 90c from previous stage quadrature demodulator lo i adc dsp or asic carrier frequency nyquist filters q adc dual matched adc figure 30. typical analog qam demodulator grounding and layout rules as is the case for any high performance device, proper ground- ing and layout techniques are essential in achieving optimal performance. the analog and digital grounds on the AD9281 have been separated to optimize the management of return currents in a system. grounds should be connected near the adc. it is recommended that a printed circuit board (pcb) of at least four layers, employing a ground plane and power p lanes, be used with the AD9281. the use of ground and power planes offers distinct advantages: 1. the minimization of the loop area encompassed by a signal and its return path. 2. the minimization of the impedance associated with ground and power paths. 3. the inherent distributed capacitor formed by the power plane, pcb insulation and ground plane. rev. f
AD9281 rev. f | page 14 of 15 revision history 1/11rev. e to rev. f updated format .................................................................. universal changes to pin configuration diagram ........................................ 4 changes to pin function descriptions table ................................ 4 removed evaluation boards; renumbered sequentially ............................................................................ 14 to 18 changes to ordering guide ........................................................... 15 8/99rev. d to rev. e
AD9281 rev. f | page outline dimensions compliant to jedec standards mo-150-ah 060106-a 28 15 14 1 10.50 10.20 9.90 8.20 7.80 7.40 5.60 5.30 5.00 seating plane 0.05 min 0.65 bsc 2.00 max 0.38 0.22 coplanarity 0.10 1.85 1.75 1.65 0.25 0.09 0.95 0.75 0.55 8 4 0 figure 33. 28-lead shrink small outline package [ssop] (rs-28) dimensions shown in millimeters ordering guide model 1, 2 temperature range package description package option AD9281ars ?40c to +85c 28-lead ssop rs-28 AD9281arsrl ?40c to +85c 28-lead ssop rs-28 AD9281arsz ?40c to +85c 28-lead ssop rs-28 AD9281arszrl ?40c to +85c 28-lead ssop rs-28 1 z = rohs compliant part. 2 rs = shrink small outline. ?1999C2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d00583-0-1/11(f)

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